da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 1 of 171 ? 2016 dialog semiconductor g eneral d escription da7217 is a high - performance, low - power audio codec optimized for use in headsets or wearable devices. it has differential headphone outputs for use inside headset devices, offering excellent left to right channel separation and common mode noise rejection. da7217 also has a stereo dac to headphone output path and ultra - low power operating modes to support always - on audio detect applications. da7217 contains two anal og microphone input paths, or up to four digital microphone input paths, or a combination of both. the other chip in this family, the da7218, has single - ended headphone outputs, and has been designed with headphone detect for use in accessories. key f eatu res high performance stereo dac to headpho ne playback path with 110 db dynamic range 4 mw stereo playback power consumption dac digital filters with audio and voice mode options, five - band equalizer and five programmable biquad stages dedicated low - latency digital sideband filter with three programmable biquad stages high performance microphone to adc record path with 105 db dynamic range 2.5 mw stereo record power consumption adc digital filters with audio and voice mode options 500 w always - on record mod e with automatic level detection hybrid analog / digital automatic level control to dynamically control the record level shutdown mode offering current consumption during standby of 2. 5 a two low - noise microphone bias regulators with programmable output voltage and ultra - low power mode a high efficiency two - level, true - ground charge pump for generating class - g headphone supplies voice mode filtering up to 32 khz flexible digital mixing from all seven inputs to all six outputs with independent gain on eac h mixer path ability to run the adcs at a different sample rate to the dacs on a single i 2 s interface digital tone generator with built - in support for dtmf system controller for simplified, pop - free start - up and shutdown phase - locked loop with sample rate tracking supporting mclk frequencies from 2 mhz to 54 mhz automatic tuning of on - chip reference oscillator for clock - free operation in low - power modes 4 - wire digital audio interface with support for i 2 s , four - channel i 2 s , tdm and other audio formats 2 - wire i 2 c compatible control interface with support for high speed mode up to 3.4 mhz 24 - bit data at up to 96 khz sample rate the headphone amplifier can be run directly from the supply, thus eliminating the need for charge pump capacitors applications hearables wireless and wired headphones wireless and wired headsets
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 2 of 171 ? 2016 dialog semiconductor system d iagram figure 1 : da7217 with d ifferential s tereo h eadphone o utputs m i c r o p h o n e i n p u t s a n a l o g o r d i g i t a l d a 7 2 1 7 a p p l i c a t i o n s p r o c e s s o r d i f f e r e n t i a l s t e r e o s p e a k e r / h e a d p h o n e d r i v e r s c o n t r o l i n t e r f a c e d i g i t a l a u d i o i n t e r f a c e
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 3 of 171 ? 2016 dialog semiconductor contents general description ................................ ................................ ................................ ............................ 1 key features ................................ ................................ ................................ ................................ ........ 1 applications ................................ ................................ ................................ ................................ ......... 1 system diagram ................................ ................................ ................................ ................................ .. 2 contents ................................ ................................ ................................ ................................ ............... 3 1 terms and definitions ................................ ................................ ................................ ................... 7 2 terminology ................................ ................................ ................................ ................................ ... 8 3 block d iagram ................................ ................................ ................................ ............................... 9 4 pinout ................................ ................................ ................................ ................................ ............. 9 4.1 input p ins ................................ ................................ ................................ ............................ 11 4.1.1 mic1_p (dmic1clk) ................................ ................................ .......................... 11 4.1.2 mic1_n (dmic1in) ................................ ................................ ............................. 11 4.1.3 mic2_p (dmic2clk) ................................ ................................ .......................... 11 4.1.4 mic2_n (dmic2in) ................................ ................................ ............................. 11 4.1.5 mclk ................................ ................................ ................................ ................... 11 4.1.6 scl ................................ ................................ ................................ ...................... 12 4.1.7 ad ................................ ................................ ................................ ........................ 12 4.1.8 datin ................................ ................................ ................................ .................. 12 4.2 output pins ................................ ................................ ................................ ......................... 12 4.2.1 nirq ................................ ................................ ................................ ..................... 12 4.2.2 datout ................................ ................................ ................................ .............. 12 4.3 bi - directional pins ................................ ................................ ................................ ............... 12 4.3.1 sda ................................ ................................ ................................ ...................... 12 4.3.2 bclk ................................ ................................ ................................ .................... 12 4.3.3 wclk ................................ ................................ ................................ ................... 12 4.4 differential headphone pins ................................ ................................ ............................... 12 4.4.1 hpl_p ................................ ................................ ................................ .................. 12 4.4.2 hpl_n ................................ ................................ ................................ ................. 12 4.4.3 hpr_p ................................ ................................ ................................ ................. 12 4.4.4 hpr_n ................................ ................................ ................................ ................. 13 4.5 charge pump pins ................................ ................................ ................................ .............. 13 4.5.1 hpcsp ................................ ................................ ................................ ................. 13 4.5.2 hpcsn ................................ ................................ ................................ ................ 13 4.5.3 hpcfp ................................ ................................ ................................ ................. 13 4.5.4 hpcfn ................................ ................................ ................................ ................. 13 4.6 references ................................ ................................ ................................ .......................... 13 4.6.1 vmid ................................ ................................ ................................ .................... 13 4.6.2 dacref ................................ ................................ ................................ .............. 13 4.6.3 vref ................................ ................................ ................................ ................... 13 4.6.4 micbias1 ................................ ................................ ................................ ............ 13 4.6.5 micbias2 ................................ ................................ ................................ ............ 13 4.6.6 vdddig ................................ ................................ ................................ ............... 13 4 .7 supply pins ................................ ................................ ................................ ......................... 14 4.7.1 vdd ................................ ................................ ................................ ..................... 14
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 4 of 171 ? 2016 dialog semiconductor 4.7.2 vdd_io ................................ ................................ ................................ ................ 14 4.7.3 vdd_mic ................................ ................................ ................................ ............. 14 4.8 ground pins ................................ ................................ ................................ ........................ 14 4.8.1 gnd ................................ ................................ ................................ ..................... 14 4.8.2 gnd_cp ................................ ................................ ................................ .............. 14 5 absolute maximum ratings ................................ ................................ ................................ ....... 15 6 recommended operating c onditions ................................ ................................ ....................... 15 7 electrical characteristics ................................ ................................ ................................ ........... 16 8 digital interfaces ................................ ................................ ................................ ......................... 23 9 functional description ................................ ................................ ................................ ............... 26 9.1 device operation ................................ ................................ ................................ ................ 26 9.1.1 power modes ................................ ................................ ................................ ....... 26 9.1.1.1 standby mode ................................ ................................ .............. 26 9.1.1.2 active mode ................................ ................................ .................. 26 9.2 input paths ................................ ................................ ................................ .......................... 26 9.2.1 microphone inputs ................................ ................................ ............................... 26 9.2.1.1 microphone biases ................................ ................................ .......... 27 9.2.1.2 microphone amplifi er ................................ ................................ ....... 28 9.2.1.3 digital microphones ................................ ................................ ......... 28 9.2.1.4 input amplifiers ................................ ................................ ................ 29 9.2.2 analog to digital converters ................................ ................................ ................ 30 9.2.2.1 high per formance mode ................................ ................................ .. 30 9.2.2.2 low - power mode ................................ ................................ ............. 30 9.2.2.3 anti - alias filters ................................ ................................ ............... 30 9.3 digital engine ................................ ................................ ................................ ...................... 31 9.3.1 input processing ................................ ................................ ................................ .. 32 9.3.1.1 input filters ................................ ................................ ...................... 32 9.3.1.2 high - pass filter ................................ ................................ ............... 33 9.3.1.3 automatic level control ................................ ................................ .. 35 9.3.1.4 input dynamic range extension ................................ ..................... 36 9.3.1.5 automa tic level control and input dynamic range extension calibration ................................ ................................ ........................ 37 9.3.1.6 level detection ................................ ................................ ................ 37 9.3.2 sidetone processing ................................ ................................ ............................ 37 9.3.3 tone generator ................................ ................................ ................................ ... 40 9.3.4 the tone generator can a lso be used to produce an s - ramp by setting swg_sel to 0x03. system controller ................................ ................................ .... 40 9.3.5 output processing ................................ ................................ ............................... 41 9.3.5.1 output filters ................................ ................................ ................... 41 9.3.5.2 high - pass filter ................................ ................................ ............... 41 9.3.5.3 5 - band equalizer ................................ ................................ ............. 43 9.3.5.4 5 - stage biquad filter ................................ ................................ ....... 45 9.3.5.5 output dynamic range exten sion ................................ .................. 48 9.3.5.6 dac noise gate ................................ ................................ .............. 48 9.3.5.7 digital mixer ................................ ................................ ..................... 49 9.3.5.8 digital gain ................................ ................................ ...................... 52 9.4 output paths ................................ ................................ ................................ ....................... 53
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 5 of 171 ? 2016 dialog semiconductor 9.4.1 digital to analog converter ................................ ................................ .................. 53 9.4.2 headphone amplifiers ................................ ................................ ......................... 53 9.4.3 charge pump contro l ................................ ................................ .......................... 56 9.4.3.1 charge pump initial and switching current ................................ .... 57 9.4.4 tracking the demands on the charge pump output ................................ .......... 57 9.4.4.1 cp_mchange = 00 (manual mode) ................................ ................... 57 9.4.4.2 cp_mchange = 01 (tracking the pga gain setting) ....................... 57 9.4.4.3 cp_mchange = 10 (tracking the dac signal setting) ..................... 57 9.4.4.4 cp_mchange = 11 (tracking the output signal magnitude) ............ 58 9.4.5 specifying clock frequencies when tracking the charge pump output demand ................................ ................................ ................................ ............... 59 9.4.6 other charge pump controls ................................ ................................ .............. 59 9.4.7 true - ground supply mode ................................ ................................ .................. 59 9.5 phase locked l oop ................................ ................................ ................................ ............ 59 9.5.1 pll bypass mode ................................ ................................ ................................ 59 9.5.2 normal pll mode (dai master) ................................ ................................ .......... 60 9.5.3 example ca lculation of the feedback divider setting: ................................ ....... 61 9.5.4 sample rate matching pll mode (dai slave) ................................ ................... 61 9.5.5 mclk input ................................ ................................ ................................ .......... 62 9.5.5.1 mclk detection ................................ ................................ ............... 62 9.5.6 audio reference oscillator ................................ ................................ .................. 62 9.5.6.1 oscillator calibration ................................ ................................ ........ 62 9.5.6.2 procedure for calibrating the re ference oscillator ......................... 63 9.5.7 internal system clock ................................ ................................ .......................... 63 9.6 reference generation ................................ ................................ ................................ ......... 63 9.6.1 voltage references ................................ ................................ ............................. 63 9.6.2 bias currents ................................ ................................ ................................ ....... 6 3 9.6.3 voltage levels ................................ ................................ ................................ ..... 63 9.6.3.1 digital regulator ................................ ................................ .............. 63 9.6.3.2 digital input/outp ut pins voltage level ................................ ........... 64 9.7 i 2 c control interface ................................ ................................ ................................ ............ 64 9.8 digital audio interface ................................ ................................ ................................ ......... 67 9.8.1 dai channels ................................ ................................ ................................ ....... 68 9.8.2 dai wclk tristate mode ................................ ................................ .................... 69 9.9 interrupt control ................................ ................................ ................................ .................. 69 9.9.1 level detect events ................................ ................................ ............................. 69 9.10 system settings ................................ ................................ ................................ .................. 70 9.10.1 sample rate ................................ ................................ ................................ ........ 70 9.10.2 gain ramp rate ................................ ................................ ................................ .. 70 9.10.3 program counter control ................................ ................................ ..................... 70 9.10.4 soft reset ................................ ................................ ................................ ............ 70 10 register maps and definitions ................................ ................................ ................................ ... 71 11 package informat ion ................................ ................................ ................................ ................. 157 12 external components ................................ ................................ ................................ ............... 158 13 ordering information ................................ ................................ ................................ ................ 158 appendix a applications information ................................ ................................ ........................... 159
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 6 of 171 ? 2016 dialog semiconductor a.1 codec initiali zation ................................ ................................ ................................ ............ 159 a.2 automatic level control calibration ................................ ................................ .................. 159 appendix b components ................................ ................................ ................................ ................ 160 b.1 audio inputs ................................ ................................ ................................ ...................... 160 b.2 microphone bias ................................ ................................ ................................ ............... 161 b.3 audio outputs ................................ ................................ ................................ ................... 161 b.4 headphone charge pump ................................ ................................ ................................ 162 b.4.1 single supply mode ................................ ................................ ........................... 162 b.5 digital interfaces ................................ ................................ ................................ ............... 163 b.6 references ................................ ................................ ................................ ........................ 164 b.7 supplies ................................ ................................ ................................ ............................ 165 b.8 ground ................................ ................................ ................................ .............................. 165 b.9 capacitor selection ................................ ................................ ................................ ........... 166 appendix c pcb layout guidelines ................................ ................................ .............................. 167 c.1 layout and schematic support ................................ ................................ ......................... 167 c.2 general recommendations ................................ ................................ .............................. 168 revision history ................................ ................................ ................................ .............................. 169
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 7 of 171 ? 2016 dialog semiconductor 1 terms and d efinitions adc analog to digital converter ags adc gain swap (input dynamic range extension) alc automatic level control anc active noise cancelling biq biquad filter cic cascaded integrator and comb dac digital to analog converter dai digital audio interface dgs dac gain swap (output dynamic range extension) dmic digital microphone dre dynamic range extension dtmf dual tone multi - frequency dwa data - weighted averager hbm hu man body model hpf high - pass filter i 2 c inter - integrated circuit interface i 2 s inter - ic sound ldo low dropout regulator lpf low - pass filter mclk master clock pc program counter pdm pulse density modulated pga programmable gain amplifier pll phase locked loop psrr power supply rejection ratio [4] rc resistance - capacitance sc system controller sdm sigma delta modulator snr signal to noise ratio [5] srm sample rate matching swg sine wave generator tdm time division multiplexing thd+n total harmonic distortion plus noise [6] vco voltage - controlled oscillator
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 8 of 171 ? 2016 dialog semiconductor 2 terminology [1] crosstalk (db) is the level difference between the active path output and the idle path measured signal level, at the test signal frequency. the active path is configured and supplied with an input signal capab le of driv ing a full scale output, with the signal measured at the output of the specified idle path. [2] mute attenuation is the difference in level between the full scale output signal and the output with mute applied. [3] channel separation (db) [ left - to - right and right - to - left ] is the difference in level between the active channel (driven to maximum full scale output) and the signal level measured in the idle channel at the test signal frequency. the active channel is configured and supplied with an input signa l capable of driv ing a full scale output, with the signal measured at the output of the associated idle channel. [4] psrr is the ratio of a given power supply change relative to the output signal that results from it. psrr is measured under quiescent signal pa th conditions. [5] snr is the difference in level between the maximum full scale output signal and the output with no input signal applied . [6] thd+n is the level of the rms value of the sum of harmonic distortion products plus noise in the specified bandwidth rel ative to the amplitude of the measured output signal. all performance measurements carried out with 20 khz low pass filter, and where noted an a - weighted filter. failure to use such a filter will result in higher thd and lower snr readings than are found in the elec trical characteristics. the low - pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 9 of 171 ? 2016 dialog semiconductor 3 block d iagram figure 2 : da7217 block diagram 4 pinout figure 3 : da7217 ballout d iagram g n d _ c p m c l k d a c r e f v m i d s d a s c l v d d d i g v d d _ i o b c l k w c l k d a t i n d a t o u t m i c 1 _ n d m i c 1 i n m i c 1 _ p d m i c 1 c l k v r e f n i r q m i c 2 _ n d m i c 2 i n m i c 2 _ p d m i c 2 c l k h p l _ n h p r _ p m i c b i a s 1 m i c b i a s 2 v d d _ m i c h p c s p h p c s n h p c f n h p c f p a d v d d g n d d i g i t a l e n g i n e d a c l p l l a d c 1 d a c r v o l t a g e r e f s l d o d i g i t a l a u d i o i n t e r f a c e d a 7 2 1 7 i n p u t f i l t e r s @ s r 1 ( h i g h - p a s s , a l c , l e v e l d e t e c t ) o u t p u t f i l t e r s @ s r 2 ( h i g h - p a s s , 5 - b a n d e q , 5 b i q u a d ) s y s t e m c o n t r o l l e r d y n a m i c r a n g e e x t e n s i o n a d c 2 4 1 2 t o n e g e n e r a t o r b i q u a d f i l t e r @ s r 2 c h a r g e p u m p i n p u t s e l e c t i o n s i d e t o n e f i l t e r @ s r 2 i 2 c c o n t r o l i n t e r f a c e h p l _ p h p r _ n 2 4 s e n s i t i v e a n a l o g u e n o i s y d i g i t a l q u a s i - s t a t i c d i g i t a l p o w e r ( u p t o 1 0 0 m a ) q u i e t g r o u n d n o i s y g r o u n d v i e w f r o m a b o v e l i v e b u g 1 a b c d 3 2 4 5 6 7 8 9 1 1 1 3 1 5 1 0 1 2 1 4 1 6 h p r _ n h p l _ p d a c r e f v m i d v d d _ m i c m i c 1 _ p h p c s p v r e f g n d _ c p h p r _ p h p l _ n v d d g n d m i c b i a s 1 m i c 1 _ n m i c b i a s 2 h p c f p h p c f n v d d _ i o d a t i n d a t o u t s c l n i r q m i c 2 _ n h p c s n v d d d i g b c l k w c l k m c l k s d a a d m i c 2 _ p
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 10 of 171 ? 2016 dialog semiconductor table 1 : da7217 p in d escription pin n o. pin n ame type ( table 2 ) description microphone i nputs a15 mic1_p dmic1clk ai/do differential analog microphone 1 input (pos) digital microphone 1 clock output b14 mic1_n dmic1in ai/di differential analog microphone 1 input (neg) digital microphone 1 data input d16 mic2_p dmic2clk ai/do differential analog microphone 2 input (pos) digital microphone 2 clock output c15 mic2_n dmic2in ai/di differential analog microphone 2 input (neg) digital microphone 2 d ata input b12 micbias1 aio microphone bias output 1 b16 micbias2 aio microphone bias output 2 headphone o utputs a5 hpl_p ao differential headphone output (left, pos) b6 hpl_n ao differential headphone output (left, neg) b4 hpr_p ao differential headphone output (right, pos) a3 hpr_n ao differential headphone output (right, neg) charge p ump a1 hpcsp aio charge pump reservoir capacitor (pos) d2 hpcsn aio charge pump reservoir capacitor (neg) c1 hpcfp aio charge pump flying capacitor (pos) c3 hpcfn aio charge pump flying capacitor (neg) digital i nterface d12 sda diod i 2 c bi - directional data c11 scl di i 2 c clock d14 ad di i 2 c slave address select (high = 1b, low = 1a) c13 nirq diod interrupt output (open drain active low) c7 datin dio dai data input to da7217 c9 datout dio dai data output from da7217 d6 bclk dio dai bit clock d8 wclk dio dai word clock d10 mclk di master clock input references a7 dacref aio dac reference decoupling capacitor a9 vmid aio mid - rail reference decoupling capacitor a11 vref aio bandgap reference decoupling capacitor linear r egulator d4 vdddig ao output from digital supply ldo
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 11 of 171 ? 2016 dialog semiconductor pin n o. pin n ame type ( table 2 ) description supplies b8 vdd ai main analog supply a13 vdd_mic ai supply for micbias ldo c5 vdd_io ai supply for digital interface and ldo b2 gnd_cp ai ground reference b10 gnd ai ground reference table 2 : pin t ype d efinition pin t ype description pin t ype description di digital input ai analog input do digital output ao analog output dio digital input/output aio analog input/output diod digital input/output open drain spu switchable pull - up resistor pu fixed pull - up resistor spd switchable pull - down resistor pd fixed pull - down resistor 4.1 input p ins 4.1.1 mic1_p (dmic1clk) mic1_p is the positive differential input for the first analog microphone channel. it can be used as a single - ended input (see figure 8 ). alternatively for digital microphones, mic1_p is used to provide a clock output. 4.1.2 mic1_n (dmic1in) mic1_n is the negative differential input for the first analog microphone channel. it can be used as a single - ended input. alternatively for digital microphon es and active noise cancelling ( anc ) applications , mic1_n is used as a pulse density modulated ( pdm ) data input. 4.1.3 mic2_p (dmic2clk) mic2_p is the positive differential input for the second analog microphone channel. it can be used as a single - ended input. a lternatively for digital microphones, mic2_p is used to provide a clock output. 4.1.4 mic2_n (dmic2in) mic2_n is the negative differential input for the second analog microphone channel. it can be used as a single - ended input. alternatively for digital microphon es and anc applications , mic2_n is used as a pdm data input. 4.1.5 mclk mclk is the master clock input pin. it is used as the main system clock either directly or via the pll.
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 12 of 171 ? 2016 dialog semiconductor 4.1.6 scl scl is the c ontrol i nterface ( i 2 c ) clock input and is used in conjunction with sda to control the device. 4.1.7 a d ad is used to select between one of two possible i 2 c slave addresses by connecting the pin to gnd or vdd_io. (high = 1b, low = 1a). 4.1.8 datin datin is the data input pin which forms part of the d igital a udio i nterface (dai) . it is us ed to present audio playback data to the device. 4.2 output p ins 4.2.1 nirq nirq is the open drain active - low interrupt output to alert the host to either an accessory or a level - detect event. 4.2.2 datout datout is the data output pin , which forms part of the dai . 4.3 bi - dir ectional p ins 4.3.1 sda sda is the c ontrol i nterface ( i 2 c ) data input/output and is used in conjunction with scl to control the device. 4.3.2 bclk bclk is the bit clock input/output pin which forms part of the dai. it is used to clock audio data bits into or out from the device or both. 4.3.3 wclk wclk is the word clock input/output pin that forms part of the dai. 4.4 differential h eadphone p ins 4.4.1 hpl_p hpl_p is the positive left - channel headphone output for a headphone speaker connected between hpl_p and hpl_n. 4.4.2 hpl_n hpl_n is the negative left - channel headphone output for a headphone speaker connected between hpl_p and hpl_n. 4.4.3 hpr_p hpr_p is the positive right - channel headphone output for a headphone speaker connected between hpr_p and hpr_n.
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 13 of 171 ? 2016 dialog semiconductor 4.4.4 hpr_n hpr_n is the negative right - chann el headphone output for a headphone speaker connected between hpr_p and hpr_n. 4.5 charge p ump p ins 4.5.1 hpcsp hpcsp is the positive output from the headphone charge pump. this pin should be connected to ground via a reservoir capacitor. 4.5.2 hpcsn hpcsn is the negative output from the headphone charge pump. if using the charge pump, this pin must be connected to ground via a reservoir capacitor. if the charge pump is not being used, then this pin should be tied directly to ground . 4.5.3 hpcfp hpcfp is one of the flying capacitor connections required by the headphone charge pump. if the charge pump is in use it must be connected to hpcfn via a capacitor. if the charge pump is not being used, then this pin can be left floating. 4.5.4 hpcfn hpcfp is one of the flyi ng capacitor connections required by the headphone charge pump. if the charge pump is in use it must be connected to hpcfp via a capacitor. if the charge pump is not being used, then this pin can be left floating. 4.6 references 4.6.1 vmid vmid is mid - rail reference decoupling capacitor connection. 4.6.2 dacref dacref is the dac reference decoupling capacitor connection. 4.6.3 vref vref is the bandgap reference decoupling capacitor connection. 4.6.4 micbias1 micbias1 is the first of two micbias outputs. this must be decoupled with a 1 f capacitor 4.6.5 micbias2 micbias2 is the second of two micbias outputs. this must be decoupled with a 1 f capacitor. 4.6.6 vdddig vdddig is the internal digital supply rail decoupling pin and is used to monitor the ldo output. this must be decoupled with a 1 f c apacitor.
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 14 of 171 ? 2016 dialog semiconductor 4.7 supply p ins 4.7.1 vdd vdd is main analog supply pin. it supplies all the analog circuits except the micbias outputs and the hpamp outputs. 4.7.2 vdd_io vdd_io is the supply pin for the digital input/output signals. 4.7.3 vdd_mic vdd_mic is the supply pin for the micbias outputs. 4.8 ground p ins 4.8.1 gnd gnd is one of the two ground reference pins (the other is gnd_cp) on the device. connect this pin to a ground plane as close as possible to the device. 4.8.2 gnd_cp gnd_cp is one of the two ground reference pins (the other is gn d) on the device. connect this pin to a ground plane as close as possible to the device.
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 15 of 171 ? 2016 dialog semiconductor 5 absolute m aximum r atings table 3 : absolute m aximum r atings ( note 1 ) parameter description conditions min max unit storage temperature C 65 +165 c t a operating temperature C 40 +85 c v dd main supply voltage C 0.3 +2.75 v v dd_io digital io supply voltage C 0.3 +5.5 v v dd_mic microphone bias supply voltage C 0.3 +5.5 v v ddio digital io pins sda, scl, ad, bclk, wclk, datin, datout, mclk , nirq C 0.3 v dd_io + 0.3 v digital microphone io pin s dmic1clk, dmic1 in C 0.3 v micbias1 + 0.3 v digital microphone io pin s dmic2clk, dmic2in - 0.3 v micbias2 + 0.3 v analog input pins mic1_p, mic1_n, mic2_p, mic2_n C 0.3 v dd + 0.3 v package thermal resistance 60 cw v esd_hbm esd susceptibility human body model (hbm) 2 kv note 1 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. exposure to absolute maximu m rating conditions for extended periods may affect device reliability. 6 recommended o perating c onditions table 4 : recommended o perating c onditions parameter description conditions min typ max unit t a operating temperature C 25 +85 c v dd main supply voltage +1.7 +2.65 v v dd_io digital io supply voltage +1.5 +3.6 v v dd_mic microphone bias supply voltage +1.8 +3.6 v
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 16 of 171 ? 2016 dialog semiconductor 7 electrical c haracteristics unless otherwise stated, test conditions are as follows: v dd = v dd_io = 1.8 v, v ddmic = 3.3 v, v dddig = 1.05 v, t a = 25 c , mclk = 12.288 mhz, sr = 48 khz, pll = bypass mode, slave mode. table 5 : power c onsumption description conditions ( note 1 ) min typ max unit powerdown mode 2.5 7 a digital playback to headphone, no load dacl/r to hp_l/r, quiescent 4 mw digital playback to headphone, with load dacl/r to hp_l/r, 32 ? load, 0.1 mw at 0 dbfs 7.7 mw microphone stereo record micl/r to adcl/r 2.5 mw microphone stereo record and digital playback to headphone, no load micl/r to adcl/r and dacl/r to hp_l/r, quiescent 5.5 mw microphone stereo record and digital playback to headphone, with load micl/r to adcl/r and dacl/r to hp_l/r, 32 ? load, 0.1 mw at 0 dbfs 8.8 mw note 1 v dd = v dd_io = v dd_mic = 1.8 v table 6 : electrical c haracteristics: microphone b ias description condition min typ max unit programmable output voltage no load, v dd_mic > v micbias + 200 mv 1.6 3.0 v output voltage step 200 mv output current output voltage droop < 50 mv 2 ma power supply rejection ratio 20 hz to 2 khz 2 khz to 20 khz 70 50 db output voltage noise v micbias 2.2 v 5 v rms table 7 : electrical c haracteristics: microphone a mplifier description condition min typ max unit full - scale input signal 0 db gain, single - ended 0.8 * v dd v pp 0 db gain, differential 1.6 * v dd input resistance 12 15 18 k programmable gain ?6 36 db gain step size 6 db absolute gain accuracy 0 db @ 1 khz - 1.0 1.0 db gain step error 20 hz to 20 khz - 0.1 0.1 db input noise level inputs connected to gnd, 24 db gain, input - referred, a - weighted 5 v rms amplitude ripple 20 hz to 20 khz - 0.5 0.5 db power supply rejection ratio 20 hz to 2 khz 2 khz to 20 khz 90 70 db
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 17 of 171 ? 2016 dialog semiconductor description condition min typ max unit crosstalk 20 hz to 20 khz 88 db table 8 : electrical c haracteristics: input a mplifier description condition min typ max unit full - scale input signal 0 db gain 1.6 * v dd v pp programmable gain ?4.5 18 db gain step size 1.5 db absolute gain accuracy 0 db @ 1 khz - 1.0 1.0 db gain step error 20 hz to 20 khz - 0.1 0.1 db amplitude ripple 20 hz to 20 khz - 0.5 0.5 db power supply rejection ratio 20 hz to 2 khz 2 khz to 20 khz 90 70 db table 9 : electrical c haracteristics: adc description condition min typ max unit full - scale input signal 0 dbfs digital output level 1.6 * v dd v pp signal to noise ratio a - weighted 90 db dynamic range adc dre enabled, a - weighted 105 db total harmonic distortion plus noise - 1 dbfs adc output level - 85 db power supply rejection ratio 20 hz to 2 khz 2 khz to 20 khz 70 50 db table 10 : electrical c haracteristics: dac description condition min typ max unit full - scale output signal 0 dbfs digital input level 1.6 * v dd v pp signal to noise ratio a - weighted 100 db dynamic range dac dre enabled, a - weighted 110 db total harmonic distortion plus noise - 1 dbfs digital input level - 90 db power supply rejection ratio 20 hz to 2 khz 2 khz to 20 khz 70 50 db table 11 : electrical c haracteristics: headphone a mplifier description condition min typ max unit full - scale output signal no load 1.6 * v dd v pp dc output offset ?30 db gain 250 v maximum output power per channel (charge pump mode) v dd = 1.8 v, thd < 0.005 %, r load = 32 ?, 1 khz 30
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 1 8 of 171 ? 2016 dialog semiconductor description condition min typ max unit v dd = 2.5 v, thd < 0.005 %, r load = 32 ?, 1 khz 58 maximum output power per channel (single supply mode) v dd = 1.8 v, thd < 0.1 %, r load = 32 ?, 1 khz 19 v dd = 2.5 v, thd < 0.1 %, r load = 32 ?, 1 khz 49 quiescent current per channel 150 a load resistance 26 32 ? load capacitance 500 pf load inductance 400 h frequency response 20 hz to 20 khz - 0.5 +0.5 db signal to noise ratio v dd = 1.8 v, 0 db gain a - weighted 98 db v dd = 2.5 v, 0 db gain a - weighted 100 db output noise level 20 hz to 20 khz, <20 db gain 2.5 v rms total harmonic distortion plus noise v dd = 1.8 v, r load = 32 ?, - 5 dbfs, 1 khz ?88 db channel separation [3] v dd = 1.8v, r load = 32 ?, 1 khz - 110 db programmable gain ?57 6 db gain step size 1.5 db absolute gain accuracy 0 db @ 1 khz ?0.8 0.8 db left/right gain mismatch 20 hz to 20 khz ?0.1 0.1 db gain step error 20 hz to 20 khz ?0.1 0.1 db amplitude ripple 20 hz to 20 khz ?0.5 0.5 db mute attenuation [2] ?70 db power supply rejection ratio 20 hz to 2 khz 2 khz to 20 khz 70 50 db crosstalk 2 khz to 20 khz 100 db table 12 : electrical c haracteristics: output a mplifier description condition min typ max unit full - scale input signal 0 dbfs output from the dac 1.6 * v dd vpp programmable gain ?1.0 0 db gain step size 0.5 db absolute gain accuracy 0 db @ 1 khz - 1.0 1.0 db amplitude ripple 20 hz to 20 khz - 0.5 0.5 db power supply rejection ratio 20 hz to 2 khz 2 khz to 20 khz 90 70 db
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 19 of 171 ? 2016 dialog semiconductor table 13 : electrical c haracteristics: input f ilters description condition min typ max unit pass band 0.45 * f s hz pass band ripple voice mode music mode 0.3 0.1 db stop band f s 48 khz f s = 88.2 khz or 96 khz 0.56 * f s 7 * f s 3.5 * f s hz stop band attenuation voice mode music mode 70 55 db group delay voice mode music mode f s = 88.2 khz or 96 khz 4.3 / f s 18 / f s 9 / f s s gain step size 0.75 db programmable gain - 83.25 12 db table 14 : electrical c haracteristics: a utomatic l evel c ontrol description condition min typ max unit attack rate f s = 48 khz 1.6 6500 db/s release rate f s = 48 khz 1.6 1675 db/s hold time f s = 48 khz 1.3 42300 ms maximum threshold ?94.5 0 dbfs minimum threshold ?94.5 0 dbfs noise threshold ?94.5 0 dbfs threshold step size 1.5 db maximum overall gain 0 90 db maximum overall attenuation 0 90 db maximum analog gain 0 36 db minimum analog gain 0 36 db gain step size 1.5 db
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 20 of 171 ? 2016 dialog semiconductor table 15 : electrical c haracteristics: dac f ilter s pecifications description conditions min typ max unit pass band 0.45 * f s hz pass band ripple voice mode music mode 0.3 0.1 db stop band f s 48 khz f s = 88.2 khz or 96 khz 0.56 * f s 7 * f s 3.5 * f s hz stop band attenuation voice mode music mode 70 55 db group delay voice mode music mode f s = 88.2 khz or 96 khz 4.3 / f s 18 / f s 9 / f s s group delay variation 20 hz to 20 khz 1 s left/right channel group delay mismatch 2 s gain step size 0.75 db programmable gain - 83.25 108 db table 16 : electrical c haracteristics: high - p ass f ilter ( i nput and o utput, adc in high - p ower m ode) out_1_voice_en / in_1_voice_en out_1_voice_hpf_corner / in_1_voice_hpf_corner out_1_audio_hpf_corner / in_1_audio_hpf_corner sr s ample r ate (khz) 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 0 00 0.33 0.46 0.5 0.67 0.92 1 1.33 1.84 2 3.68 4 01 0.67 0.92 1 1.33 1.84 2 2.67 3.68 4 7.35 8 10 1.33 1.84 2 2.67 3.68 4 5.33 7.35 8 14.7 16 11 2.67 3.68 4 5.33 7.35 8 10.67 14.7 16 29.4 32 1 000 2.5 3.45 3.75 5 6.89 7.5 10 voice hpf not available for sample rates above 32 khz. 001 25 34.5 37.5 50 68.9 75 100 010 50 68.9 75 100 137.8 150 200 011 100 137.8 150 200 275.6 300 400 100 150 206.7 225 300 413.4 450 600 101 200 275.6 300 400 551.3 600 800 110 300 413.4 450 600 826.9 900 1200 111 400 551.3 600 800 1102.5 1200 1600
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 21 of 171 ? 2016 dialog semiconductor table 17 : high - p ass f ilter s ettings (adc in low - p ower m ode) in_1_voice_en out_1_voice_en in_1_voice_hpf_corner out_1_voice_hpf_corner in_1_audio_hpf_corner out_1_audio_hpf_corner . sr s ample r ate (khz) 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 0 00 0.33 0.46 0.5 0.67 0.92 1 32 khz sample rate not available in l ow - p ower mode 1.84 2 88.2 khz and 96 khz sample rates not available in l ow - p ower mode 01 0.67 0.92 1 1.33 1.84 2 3.68 4 10 1.33 1.84 2 2.67 3.68 4 7.35 8 11 2.67 3.68 4 5.33 7.35 8 14.7 16 1 000 2.5 in low - power mode, the voice hpf is only available at a sample rate of 8 khz 001 25 010 50 011 100 100 150 101 200 110 300 111 400 table 18 : electrical c haracteristics: 5 - b and equalizer fs (khz) cente r f requency (hz) a t p rogrammed s etting band 1 band 2 band 3 band 4 band 5 8 0 99 493 1528 4000 11.025 0 136 680 2106 5512 12 0 148 740 2293 6000 16 0 96 440 2128 8000 22.05 0 133 607 2933 11025 24 0 145 660 3191 12000 32 0 95 418 1797 16000 44.1 0 131 576 2386 22050 48 0 143 627 2596 24000 88.2 not available 96
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 22 of 171 ? 2016 dialog semiconductor figure 4 : 5 - b and equalizer r esponse at 48 khz table 19 : pll m ode description conditions min typ max unit mclk input jitter absolute jitter (rms) ( note 1 ) 540 ps mclk input frequency normal mode 2 54 mhz srm tracking range dai slave mode wclk frequency variation - 4 4 % srm tracking rate dai slave mode wclk drift rate 54 ppm/s note 1 jitter in the 100 hz to 40 khz band table 20 : bypass m ode description conditions min typ max unit mclk input jitter absolute jitter (rms) ( note 1 ) 540 ps mclk input frequency f s = 11.025, 22.05, 44.1, 88.2 khz f s = 8, 12, 16, 24, 32, 48, 96 khz 11.2896 12.288 mhz note 1 jitter in the 100 hz to 40 khz band table 21 : tone g enerator description conditions min typ max unit single - tone frequency f s = 8, 12, 16, 24, 32, 48, 96 khz f s = 11.025, 22.05, 44.1, 88.2 khz 1 1 12000 11025 hz single - tone frequency step f s = 8, 12, 16, 24, 32, 48, 96 khz f s = 11.025, 22.05, 44.1, 88.2 khz 0.18 0.17 hz
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 23 of 171 ? 2016 dialog semiconductor description conditions min typ max unit dual - tone modulation frequency a 697 770 852 941 hz dual - tone modulation frequency b 1209 1336 1477 1633 hz output signal level 0 dbfs on/off pulse duration 10 2000 ms on/off pulse step size 10 ms to 200 ms duration 200 ms to 2000 ms duration 10 50 ms on/off pulse repeat programmable continuous 1, 2, 3, 4, 5, 6 cycles 8 digital i nterfaces table 22 : i/o c haracteristics parameter description conditions min typ max unit v ih scl, sda, mclk, bclk, wclk, datin, datout , ad input high voltage 0.7 * v dd_io v v il scl, sda, mclk, bclk, wclk, datin, datout input low voltage 0.3 * v dd_io v v ol sda , nirq output low voltage i o ut = 3 ma 0.24 v v oh dmic1clk output high voltage 0.7 * v micbias1 v ol dmic1clk output high voltage 0.3 * v micbias1 v ih dmic1in input high voltage 0.7 * v micbias1 v il dmic1in input low voltage 0.3 * v micbias1 v oh dmic2clk output high voltage 0.7 * v micbias2 v ol dmic2clk output low voltage 0.3 * v micbias2 v ih dmic2in input high voltage 0.7 * v micbias2 v il dmic2in input low voltage 0.3 * v micbias2
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 24 of 171 ? 2016 dialog semiconductor figure 5 : i 2 c b us t iming table 23 : i 2 c c ontrol b us (vdd_io = 1.8 v) parameter description conditions min typ max unit bus free time stop to start 500 ns bus line capacitive load 150 pf standard/fast m ode scl clock frequency 0 1000 khz start condition setup time 260 ns sth start condition hold time 260 ns clkl scl low time 500 ns clkh scl high time 260 ns scl rise/fall time input requirement 1000 ns sda rise/fall time input requirement 300 ns dst sda setup time 50 ns dht sda hold time 0 ns tss stop condition setup time 260 ns high - s peed m ode scl clock frequency 0 3400 khz start condition setup time 160 ns sth start condition hold time 160 ns clkl scl low time 160 ns clkh scl high time 60 ns scl rise/fall time input requirement 160 ns sda rise/fall time input requirement 160 ns dst sda setup time 10 ns dht sda hold time 0 ns tss stop condition setup time 160 ns s c l s d a s t h c l k l c l k h d s t t s s d h t
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 25 of 171 ? 2016 dialog semiconductor figure 6 : dai t iming d iagram note diagram shown is valid for all modes except dsp. for dsp mode the bclk signal is inverted table 24 : dai t iming ( i 2 s / dsp in master/ s lave m ode) parameter description conditions (vdd_io = 1.8 v) min typ max unit input impedance dc impedance > 10 m? 300 1.0 2.5 ? pf t bclk period 75 ns tr bclk rise time 8 ns tf bclk fall time 8 ns thc bclk high period 40 % 60 % t tlc bclk low period 40 % 60 % t tdcw bclk to wclk delay - 30 % +30 % t tdcd bclk to datout delay - 30 % +30 % t thw wclk high time dsp mode 100 % t non - dsp mode word length ( note 1 ) t tlw wclk low time dsp mode 100 % t non - dsp mode word length ( note 2 ) t tsw wclk setup time slave mode 7 ns thw wclk hold time slave mode 2 ns tsd datin setup time 7 ns thd datin hold time 2 ns tdwd datout to wclk delay datout is synchronized to bclk note 1 wclk must be high for at least the word length number of bclk periods note 2 wclk must be low for at least the word length number of bclk periods t t l c t h c b c l k d a t i n t f t s d d a t o u t w c l k t r t d c w t d c d t d w d t h d t s w t h w
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 26 of 171 ? 2016 dialog semiconductor 9 functional d escription da7217 is a high - performance, low - power audio codec optimized for use in headsets or wearable devices. it contains two analog microphone - to - adc and/or up to four digital microphone - to - input filter paths, and a dai for input and output. da7217 has differential headphone outputs for use inside headset devices, offerin g excellent left to right channel separation and common mode noise rejection. the other chip in this family, the da7218, has single - ended headphone outputs, and has been designed with headphone - detect for use in accessories. the digital engine input includ es a high pass filter, automatic level control (alc), and level detection. the output stage has a high pass filter, a 5 - band eq, and a 5 - stage biquad filter. the digital engine also has a dynamic range extension (dre) block, and a tone generator that suppo rts dual tone multi - frequency (dtmf). the flexible digital mixer allows any or all of the seven inputs (four input filters, the tone generator, and dai left and right inputs) to be routed to any or all of the six digital outputs (left and right output filt ers, and dai outputs). there is an independently programmable gain on each of the 42 possible paths. 9.1 device o peration 9.1.1 power m odes the da7217 codec has two operating modes: standby C the device is asleep with all internal circuits disabled, but all register states are retained. active C the device is awake and ready to perform audio functions. blocks can be enabled as required. 9.1.1.1 standby m ode in standby mode, both the reference voltage generator and the reference oscillator are shut down so no audio functions are possible. all audio paths must be shut down before entering standby mode ( system_active = 0), as the transition to standby mode is immediate and is not pop - free. 9.1.1.2 active m ode to put the device in active mode, write system_active = 1. on entering active mode, the reference voltage generator and reference o scillator are automatically enabled. 9.2 input p aths 9.2.1 microphone i nputs the da7217 analog inputs consist of two independent signal chains, each including two amplifiers and an adc as shown in figure 7 .
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 27 of 171 ? 2016 dialog semiconductor figure 7 : analog i nputs b lock d iagram the two microphone amplifiers can be configured in fully differential mode for improved common - mode noise rejection pseudo - differential mode single - ended mode (mic1|2_p or mic1|2_n) all configurations are illustrated in figure 8 . digital microphone connection details are described in section 9.2.1.3 . 9.2.1.1 microphone b iases the da7217 codec has two independently controlled microphone bias outputs. low n oise ( n ormal) m ode each bias output can be independently programmed from 1.6 v to 3.0 v in 0.2 v steps using micbias_1_level and micbias_2_level in micbias_ctrl . each microphone bias level can only be changed while the associated micbias circuit is disabled ( micbias_1_en = 0 for micbias1 or micbias_2_en = 0 for micbias2). low - p ower m ode both microphone bias circuits can also be used as low - power voltage sources optimized for always - on microphones. in low - power mode the output voltage is fixed at 1.2 v. l ow - power mode is enabled by setting the micbias_1_lp_mode = 1 in the micbias_ctrl register. micbias1 is enabled by setting micbias_1_en = 1. the second microphone bias circuit (micbias2) is controlled in the same way. low - power mode can only be changed while the micbias circuits are disabled ( micbias_1_en = 0 for low - power mode on micbias1, and micbias_2_en = 0 for low - power mode on micbias2). table 25 : microphone b ias s ettings micbias_1_level micbias_2_level output v oltage in l ow - n oise m ode micbias_1|2 _lp_mode = 0 (v) output v oltage in l ow - p ower m ode micbias_1|2_lp_mode = 1 (v) 000 1.6 1.2 001 1.8 010 2.0 011 2.2 100 2.4 101 2.6 110 2.8 111 3.0 t o a d c 2 l f i l t e r a d c 1 a d c 2 t o a d c 1 l f i l t e r m i c _ 1 _ a m p ? 6 : + 6 : + 3 6 d b m i x i n _ 1 _ a m p ? 4 . 5 : + 1 . 5 : + 1 8 d b m i c _ 2 _ a m p ? 6 : + 6 : + 3 6 d b m i x i n _ 2 _ a m p ? 4 . 5 : + 1 . 5 : + 1 8 d b m i c 1 _ n m i c 1 _ p m i c 2 _ n m i c 2 _ p
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 28 of 171 ? 2016 dialog semiconductor 9.2.1.2 microphone a mplifier figure 8 : analog m icrophone c onfigurations the configuration of the first microphone amplifier ( mic_1_ctrl ) is specified using mic_1_amp_in_sel . it is enabled by setting mic_1_amp_en = 1 , and is muted by setting mic_1_amp_mute_en = 1. the gain of the amplifier can be set in the range of C 6 db to +36 db in 6 db steps using mic_1_amp_gain (see table 26 : ). the second microphone amplifier ( mic_2_ctrl ) is controlled in the same way. table 26 : mic_1_gain and mic_2_gain g ain s ettings mic_1_amp_gain mic_2_amp_gain amplifier g ain (db) 000 - 6 001 0 010 6 011 12 100 18 101 24 110 30 111 36 9.2.1.3 digital m icrophones the da7217 can support up to four digital microphones by reusing the mic1_p and mic_2p pins as clock outputs, and the mic1_n and mic_2n pins as digital data inputs. the io voltage level of dmic1 is set by the voltage present on micbias1 and the io voltage level of d mic2 is set by the voltage present on micbias2. this voltage can be either an output of the micbias ldo or, for minimum power consumption, the io voltage of the dmic can be connected as an input on the appropriate micbias pin. the first dmic input is contr olled using the dmic_1_ctrl register. the left channel is enabled using dmic_1l_en and the right channel using dmic_1r_en . the dmic clock rate can be set to either 3 mhz or 1.5 mhz using dmic_1_clk_rate . dmic_1 data is sampled on both the rising and the falling edges of the dmic clock. the register field dmic_1_data_sel determines which of the rising and the falling edges corresponds to the left channel, and which to the right. the register field dmic_1_samplephase controls whether the sample point for the dmic data is on the dmicclck edges ( dmic_1_samplephase = 0) or at the midpoint between the dmicclck edges ( dmic_1_samplephase = 1). m i c b i a s 1 | 2 m i c 1 | 2 _ p m i c 1 | 2 _ n m i c b i a s 1 | 2 m i c 1 | 2 _ p m i c 1 | 2 _ n m i c b i a s 1 | 2 m i c 1 | 2 _ p ( a ) d i f f e r e n t i a l ( b ) p s e u d o - d i f f e r e n t i a l ( c ) s i n g l e - e n d e d m i c 1 | 2 _ n
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 29 of 171 ? 2016 dialog semiconductor the second dmic input is controlled in the same way using dmic_2_ctrl . table 27 : digital m icrophone c ontrol b its function register b its bit s etting 0 1 digital microphone enable/disable dmic_1r_en dmic_1l_en dmic_2l_en dmic_2r_en dmic is disabled dmic is enabled digital microphone clock rate dmic_l_clk_rate dmic_2_clk_rate 3 mhz 1.5 mhz digital microphone sample phase dmic_1_samplephase dmic_2_samplephase data sa mpled on the clock edges data sampled between the clock edges digital microphone left/right data selection dmic_1_data_sel dmic_2_data_sel rising edge = left falling edge = right rising edge = right falling edge = left 9.2.1.4 input a mplifiers the two input amplifiers provide an additional gain stage between the microphone amplifiers (see section 9.2.1.2 and figure 7 ) and the adc inputs. the input amplifier ( mixin_1_ctrl ) is enabled by se tting mixin_1_amp_en = 1. the gain can be set in the range of C 4.5 db to +18 db in 1.5 db steps using mixin_1_gain . it is recommended that g ain updates be ramped through all intermediate values by setting mixin_1_amp_ramp_en = 1. this ramp setting overrides the settings of mixin_1_amp_zc_en . as an alternative to ze ro - cross synchronization , gain updates can be synchronized with signal zero - crossings by setting mixin_1_amp_zc_en = 1. if no zero - crossing is detected with in the timeout period of approximately 100 ms, the update is applied unconditionally. the amplifier can be muted using mixin_1_amp_mute_en .the single inpu t to the first amplifier can be deselected by setting mixin_1_mix_sel = 0. the second input amplifier ( mixin_2_ctrl ) is controlled in the same manner as mixin_1_ctrl . table 28 : mixin_1_gain and mixin_2_gain g ain s ettings mixin_1_amp_gain mixin_2_amp_gain amplifier g ain (db) 0000 - 4.5 0001 - 3.0 0010 - 1.5 0011 0.0 0100 1.5 0101 3.0 0110 4.5 0111 6.0 1000 7.5 1001 9.0 1010 10.5
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 30 of 171 ? 2016 dialog semiconductor mixin_1_amp_gain mixin_2_amp_gain amplifier g ain (db) 1011 12.0 1100 13.5 1101 15.0 1110 16.5 1111 18.0 9.2.2 analog to d igital c onverters the da7217 codec contains the stereo audio analog to digital converters (adcs). these can run either in low - power mode for always - on applications, or in high performance mode for other applications. each adc is automatically enabled whenever the input filters are e nabled and digital microphones are not enabled. not all sample rates are supported in all modes. table 29 describes which sample rates are supported in each mode. table 29 : supported s ample r ates in d ifferent m odes sample r ate (khz) low power m ode adc_lp_mode = 1 normal m ode adc_lp_mode = 0 voice_en = 1 voice_en = 0 voice_en = 1 voice_en = 0 8.0 supported supported supported supported 11.025/12.0 not supported supported supported supported 16.0 not supported supported supported supported 22.050/24.0 not supported supported supported supported 32.0 not supported not supported supported supported 44.100/48.0 not supported supported not supported supported 88.200/96.0 not supported not supported not supported supported 9.2.2.1 high p erformance m ode in normal (high performance) mode ( adc_lp_mode = 0), the adcs are clocked at a fixed rate of either 3.072 mhz or 2.8224 mhz, depending on the required input sample rate (sr1). 9.2.2.2 low - p ower m ode the low - power mode of operation is designed for a lways - on applications. in low - power mode, the adcs are clocked at half the normal (high - performance) rate, that is, at either 1.5360 mhz or 1.4112 mhz. low - power mode is set in both adcs by setting adc_lp_mode = 1. in this mode there is a small increase in distortion. 9.2.2.3 anti - a lias f ilters the anti - alias filters at the front - end of the adc are enabled by default. the anti - alias filters can be disabled to save power by setting adc_1_aaf_en = 0 for channel 1, or adc_2_aaf_en = 0 for channel 2.
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 31 of 171 ? 2016 dialog semiconductor 9.3 digital e ngine the da7217 chip contains a digital engine that performs the signal processing and also provides overall system control. within the digital engine, all seven po ssible input signals can be mixed and output to any of the six possible outputs. see figure 9 for a visual representation of this. the output signals f rom either of the two adcs or any of the four digital microphones are passed to the input filter block. the filter block includes a high - pass filter for wind noise suppression, an automatic level control, and input level detection. the signals from the inp ut filters are sent to the digital mixer where they can be combined with signals from the tone generator and the dai , and routed to the output filters and the dai. the output filters contain a high - pass filter for dc offset removal, a fixed 5 - band equalize r , and a flexible 5 - stage biquad filter to adjust the sound of the output signals. there is also a sidetone path that can take one signal from either the adcs or the digital microphones and perform filtering using three biquad sections before passing the s ignal straight to the output filters. the digital engine contains a dre module that can be used to automatically swap analog and digital gains on the input and output signal paths in order to maximize the dynamic range of the codec. finally a system controller module is included to ensure correct sequencing of the events required to bring up and shut down signal paths without creating pops and clicks. figure 9 : digital e ngine b lock d iagram d i g i t a l e n g i n e i n p u t f i l t e r s @ s r 1 ( h i g h - p a s s , a l c , l e v e l d e t e c t ) o u t p u t f i l t e r s @ s r 2 ( h i g h - p a s s , 5 - b a n d e q , 5 b i q u a d ) s y s t e m c o n t r o l l e r d y n a m i c r a n g e e x t e n s i o n 4 1 2 2 t o n e g e n e r a t o r 3 b i q u a d s i d e t o n e f i l t e r @ 4 s r 2 i n p u t s e l e c t i o n 4 a d c 1 / d m i c 1 l d m i c 1 r a d c 2 / d m i c 2 l d m i c 2 r d i g i t a l a u d i o i n t e r f a c e ( d a i ) d a c l d a c r
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 32 of 171 ? 2016 dialog semiconductor 9.3.1 input p rocessing 9.3.1.1 input f ilters figure 10 : input f ilters b lock d iagram there are two stereo pairs of input filters ( in_1l_filter_ctrl and in_1r_filter_ctrl , and in_2l_filter_ctrl and in_2r_filter_ctrl ) that can be used to process signals from either the two mono adcs, or from the two stereo digital microphone inputs. the input (adc or dmic) to the input filters is selected using dmic_1l_en (or dmic_1r_en ) and dmic_2l_en (or dmic_2r_en ). if an adc input is selected, the analog part of the adc is enabled whenever the dmic has not been enabled and the connected input filter has been enabled using one of the filter enabling bits ( in_1l_filter_en , in_1r_filter_en , in_2l_filter_en , and in_2r_filter_en ). left and right channels of the two input filters can be controlled independently. the left channel of the first input filter is enabled using in_1l_filter_en . it is muted using in_1l_mute_en and gain - ramping is enabled using in_1l_ramp_en . the gain can be set in the range of C 83.25 db to +12 db in +0.75 db steps using in_1l_digital_gain . the right channel and the second input filter channels are all controlled in the same way. c i c c i c i n _ 1 l _ f i l t e r i n _ 1 r _ f i l t e r f s d m 4 f s 1 2 f s 1 f s 1 c i c c i c i n _ 2 l _ f i l t e r i n _ 2 r _ f i l t e r f s d m 4 f s 1 2 f s 1 f s 1 a d c 1 / d m i c 1 l d m i c 1 r d m i c 2 r a d c 2 / d m i c 2 l i n 1 l i n 1 r i n 2 l i n 2 r d i g i t a l e n g i n e i n p u t s e l e c t i o n
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 33 of 171 ? 2016 dialog semiconductor ta ble 30 : in_filt d igital g ain s ettings in_1l_digital_gain , in_1r_digital_gain , in_2l_digital_gain in_2r_digital_gain setting gain (db) in_1l_digital_gain , in_1r_digital_gain , in_2l_digital_gain , in_2r_digital_gain setting gain (db) in_1l_digital_gain , in_1r_digital_gain , in_2l_digital_gain , in_2r_digital_gain setting gain (db) binary hex binary hex binary hex 0000000 0x00 - 83.25 0101011 0x2b - 51 1010110 0x56 - 18.75 0000001 0x01 - 82.5 0101100 0x2c - 50.25 1010111 0x57 - 18 0000010 0x02 - 81.75 0101101 0x2d - 49.5 1011000 0x58 - 17.25 0000011 0x03 - 81 0101110 0x2e - 48.75 1011001 0x59 - 16.5 0000100 0x04 - 80.25 0101111 0x2f - 48 1011010 0x5a - 15.75 0000101 0x05 - 79.5 0110000 0x30 - 47.25 1011011 0x5b - 15 0000110 0x06 - 78.75 0110001 0x31 - 46.5 1011100 0x5c - 14.25 0000111 0x07 - 78 0110010 0x32 - 45.75 1011101 0x5d - 13.5 0001000 0x08 - 77.25 0110011 0x33 - 45 1011110 0x5e - 12.75 0001001 0x09 - 76.5 0110100 0x34 - 44.25 1011111 0x5f - 12 continuing in 0.7 5 db steps until 0011110 0x1e - 60.75 1001001 0x49 - 28.5 1110100 0x74 3.75 0011111 0x1f - 60 1001010 0x4a - 27.75 1110101 0x75 4.5 0100000 0x20 - 59.25 1001011 0x4b - 27 1110110 0x76 5.25 0100001 0x21 - 58.5 1001100 0x4c - 26.25 1110111 0x77 6 0100010 0x22 - 57.75 1001101 0x4d - 25.5 1111000 0x78 6.75 0100011 0x23 - 57 1001110 0x4e - 24.75 1111001 0x79 7.5 0100100 0x24 - 56.25 1001111 0x4f - 24 1111010 0x7a 8.25 0100101 0x25 - 55.5 1010000 0x50 - 23.25 1111011 0x7b 9 0100110 0x26 - 54.75 1010001 0x51 - 22.5 1111100 0x7c 9.75 0100111 0x27 - 54 1010010 0x52 - 21.75 1111101 0x7d 10.5 0101000 0x28 - 53.25 1010011 0x53 - 21 1111110 0x7e 11.25 0101001 0x29 - 52.5 1010100 0x54 - 20.25 1111111 0x7f 12 0101010 0x2a - 51.75 1010101 0x55 - 19.5 9.3.1.2 high - p ass f ilter the da7217 contains two stereo input high - pass filters (hpfs). the first filter is controlled using in_1_hpf_filter_ctrl and in_2_hpf_filter_ctrl to remove any dc components from the incoming audio. this filter op erates at all sample rates. for this first filter, in music mode in_1_voice_en must be set to 0 and the hpf corner frequency is set using in_1_audio_hpf_corner . a second high pass filter is available when the sample rate is 32 khz or lower for voice filtering . this filter is controlled using in_1_voice_en and in_2_voice_en . it has a wider range of corner frequ encies to help remove low frequency artefacts such as wind noise. in voice mode, in_1_voice_en must = 1 in which case the hpf corner frequency is set using in_1_voice_en . the value of th e hpf corner frequency also depends on the input sample rate (sr1) as shown in table 31 (adc in high power mode) and table 32 (adc in low power mode). note that when operating in adc low power mode ( adc_lp_mode = 1), the voice filter is only available at a sample rate of 8 khz. similarly the audio filter will not operate at sample rates of 32 khz, 88.2 khz, or 96 khz. the sample rates available in the different adc power modes are summarized in table 31 for the adc in high - power mode ( adc_lp_mode = 0), and table 32 for the adc in low - power mode ( adc_lp_mode = 1).
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 34 of 171 ? 2016 dialog semiconductor table 31 : input h igh - p ass f ilter s ettings (adc in h igh - p ower m ode) in_1_voice_en out_1_voice_en in_1_voice_hpf_corner out_1_voice_hpf_corner in_1_audio_hpf_corner out_1_audio_hpf_corner sample r ate (khz) 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 0 00 0.33 0.46 0.5 0.67 0.92 1 1.33 1.84 2 3.68 4 01 0.67 0.92 1 1.33 1.84 2 2.67 3.68 4 7.35 8 10 1.33 1.84 2 2.67 3.68 4 5.33 7.35 8 14.7 16 11 2.67 3.68 4 5.33 7.35 8 10.67 14.7 16 29.4 32 1 000 2.5 3.45 3.75 5 6.89 7.5 10 voice hpf not available for sample rates above 32 khz. 001 25 34.5 37.5 50 68.9 75 100 010 50 68.9 75 100 137.8 150 200 011 100 137.8 150 200 275.6 300 400 100 150 206.7 225 300 413.4 450 600 101 200 275.6 300 400 551.3 600 800 110 300 413.4 450 600 826.9 900 1200 111 400 551.3 600 800 1102.5 1200 1600 table 32 : input h igh - p ass f ilter s ettings (adc in l ow - p ower m ode) in_1_voice_en out_1_voice_en in_1_voice_hpf_corner out_1_voice_hpf_corner in_1_audio_hpf_corner out_1_audio_hpf_corner . sample rate (khz) 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 0 00 0.33 0.46 0.5 0.67 0.92 1 32 khz sample rate not available in low - power mode 1.84 2 88.2 khz and 96 khz sample rates not available in low - power mode 01 0.67 0.92 1 1.33 1.84 2 3.68 4 10 1.33 1.84 2 2.67 3.68 4 7.35 8 11 2.67 3.68 4 5.33 7.35 8 14.7 16 1 000 2.5 in low - power mode, the voice hpf is only available at a sample rate of 8 khz 001 25 010 50 011 100 100 150 101 200 110 300 111 400
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 35 of 171 ? 2016 dialog semiconductor 9.3.1.3 automatic l evel c ontrol for improved sound recordings of signals with a large volume range, the da7217 offers a fully - configurable automatic recording level control (alc) for microphone inputs. this is enabled via the alc_ctrl1 , and can be enabled independently on any of the four input channels. the alc monitors the digital signal after the adc and adjusts the microphones analog and digital gain to maintain a constan t recording level, regardless of the analog input signal level. operation of alc is illustrated in figure 11 . when the input signal volume is high, th e alc system will reduce the overall gain until the output volume is below the specified maximum value. when the input signal volume is low, the alc will increase the gain until the output volume increases above the specified minimum value. if the output s ignal is within the desired signal level (between the specified minimum and maximum levels), the alc does nothing. the minimum and the maximum thresholds that trigger a gain change of the alc are programmed by the alc_thre shold_min and alc_threshold_max controls. figure 11 : principle of o peration of the alc the alc can operate in two modes; digital - only mode and hybrid ( combined a nalog and digital gain ) mode. in digital - o nly mode only the digital gain in the adc is altered. note that although the alc is controlling the gain, it does not modify any of the registers in_1l_digital_gain , in_1r_digital_gain , in_2l_digital_gain , or in_2r_digital_gain . these registers are ig nored while the alc is in operation. the minimum and maximum levels of digital gain that can be applied by the alc are controlled using alc_atten_max and alc_gain_max . when using analog microphones, hybrid mode can be enabled using alc_sync_mode . see section 9.3.1.5 for details on alc calibration in hybrid mode. in hybrid mode, the total gain is made u p of an analog gain ( which is applied to the microphone amplifiers ) and a digital gain, ( which is implemented in the filtering stage ) .the alc block monitors and controls the gain of the microphone and the adc. note that although the alc is controlling the gain, it does not modify any of the registers mixin_1_amp_gain or mixin_2_amp_gain , nor does it modify any of the digital gain registers in_1l_digital_gain , in_1r_digital_gain , in_2l_digital_gain , or in_2r_digital_gain . these registers are ignored while the alc is in operation. a l c i n p u t a l c g a i n a l c o u t p u t a l c m a x l e v e l a l c m i n l e v e l r e l e a s e t i m e a t t a c k t i m e
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 36 of 171 ? 2016 dialog semiconductor similarly the minimum and maximum levels of analog gain are controlled by alc_ana_gain_min and alc_ana_gain_max . the rates at which the gain is changed are d efined by the attack and decay rates in register alc_ctrl2 . when attacking, the gain decreases with alc_attack rate. when decaying, the gain increases with alc_release rate. hybrid mode should be used wh enever analog microphones are being used. digital - o nly mode should be used whenever digital microphones are being used. the hold - time is defined by alc_hold in the alc_ctrl3 register. this controls the length of time that the system maintains the current gain level before starting to decay. this prevents unw anted changes in the recording level when there is a short - lived spike in input volume, for example when recording speech. typically the attack rate should be much faster than the decay rate. to avoid clipping i t is necessary to reduce rapidly increasin g waveforms as quickly as possible, whereas fast release times will result in the signal appearing to pump. the alc also has an anti - clip function that applies a very fast attack rate when the input signal is close to full - scale. this prevents clipping o f the signal by reducing the signal gain at a faster rate than would normally be applied. the anti - clip function is enabled using alc_anticlip_en , and the trigger threshold is set in the range 0.034 db/ f s to 0.272 db/ f s using alc_anticlip_step . a recording noise - gate feature is provided to avoid increasing the gain of the channel when there is no signal, or when only a noise signal is present. boosting a signal on which only noise is present is known as noise pumping, the noise - gate prevents this. whenever the level of the input signal drops below the noise threshold configured in alc_noise , the channel gain remains constant. figure 12 : attack, d elay and h old p arameters 9.3.1.4 input d ynamic r ange e xtension when using analog microphones, t he input dynamic range extension (dre) automatically swaps the analog and d igital gains to maximize the dynamic range at all times. m a x m i n a t k d c y h l d i n p u t s i g n a l g a i n l e v e l a t k r a t e d c y r a t e t i m e t i m e
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 37 of 171 ? 2016 dialog semiconductor the dre block, like the hybrid - mode alc, controls both the analog micamp gain and the digital gain. however it applies equal and opposite adjustments to analog and digital gains so that total path gain remains constant while the input dynamic range is increased. dre can be enabled for either or both adcs using the ags_enable bits. the trigger level f or the dre can be set in the range of C 90 db to 0 db in 6 db steps using ags_trigger . the maximum attenuation that can be applied by the dre can be set in the range of 0 db to 36 db in 6 db steps using ags_att_max . there is also a timeout of 0.1 s that can be enabled using ags_timeout_en , and a mechanism to prevent clipping that can be enabled using ags_anticlip_en . note that t he input dre cannot be used with alc. only one of these functions can be used at any one time . 9.3.1.5 a utomatic l evel c ontrol and i nput d ynamic r ange e xtension c alibration when using the alc in hybrid mode or when using the input dre, the dc offset at the output of the micamps must be compensated for to prevent audible effects when the gains are changed. this compensation is performed automatically if the following sequence is followed: 1. enable the required micamp(s) unmuted . 2. mute the m icamp(s). note that it is important to enable the micamps unmuted before using them in this step . 3. enable the required mixin_1|2_amp(s) and adc(s) unmuted . 4. enable the dai or set the pc to freerun mode . 5. set calib_auto_en to 1 to start the calibration. this bit will clear to 0 once the calibration is complete . 6. set calib_offset_en to 1 . 7. enable the alc in hybrid mode or the dre. note that alc and input dre are mutually exclusive, and only one should be enabled at any one time . 8. unmute the micamp(s) . 9.3.1.6 level d etection level detection can be used to signal to the host processor (via the nirq pin) that the input signal has exceeded the threshold level determined by lvl_det_level . level detection can be enabled on any or all of the four input filter channels using the lvl_det_en bits. the threshold used for level detection ca n be programmed in the range of 1/128 full - scale to full - scale using lvl_det_level . 9.3.2 sidetone p rocessing there is a mono, low - latency filter channel between inputs and outputs for implementing a sidetone path. the input signal to any one of the four input channels (from dmic or adc) can also be routed to the sidetone channel using sidetone_in_select . the output from the sidetone channel can be added to left or right (or both) output filters using outfilt_st_1l_src and outfilt_st_1r_src . the sidetone filter itself contains a three - stage biquad filter that can be used to provide custom filtering of the input signal. the biquad filter also has a programmable gain stage to adjust the level of the sidetone signal. this is controlled by sidetone_gain , and provides gain in the range - 42 db to +4.5 db in 1.5 db steps. the sidetone path is enabled using sidetone_filter_en . and muted using sidetone_mute_en . figure 13 : sidetone f ilter b lock d iagram c i c 3 b i q u a d g a i n s t a g e s i d e t o n e _ f i l t e r f s d m 4 f s 2
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 38 of 171 ? 2016 dialog semiconductor the sidetone biquad filter can be used to provide custom filtering, for example microphone frequency response. each of the three biquad stages has five 16 - bit coefficients a0, a1, a2, b1 and b2 (see figure 21 ). for the three stages, the coefficients are numbered a00, a01 etc. as shown in figure 14 : figure 14 : cascade of t hree b iquad f ilter s tages the coefficients are stored using 8 - bit registers in a dedicated address space. they are programmed by first writing the coefficient data value to sidetone_biq_3stage_data and then the coefficient address to sidetone_biq_3stage_addr . the address location for each of the coefficients is described in table 33 : each of the 16 - bit coefficients is twos co mplement values that are programmed in the range of - 2 (0x8000) to +2 (0x7fff). it is the responsibility of the user to ensure that filter transfer function corresponding to the programmed coefficients is stable. table 33 : sidetone 3 - s tage b iquad f ilter c oefficient a ddress m ap address name description 0x00 sidetone_biq_a00_lo lower byte of a00 coefficient for first sidetone biquad stage 0x01 sidetone_biq_a00_hi upper byte of a00 coefficient for first sidetone biquad stage 0x02 sidetone_biq_a01_lo lower byte of a01 coefficient for first sidetone biquad stage 0x03 sidetone_biq_a01_hi upper byte of a01 coefficient for first sidetone biquad stage 0x04 sidetone_biq_a02_lo lower byte of a02 coefficient for first sidetone biquad stag e 0x05 sidetone_biq_a02_hi upper byte of a02 coefficient for first sidetone biquad stage 0x06 sidetone_biq_b01_lo lower byte of b01 coefficient for first sidetone biquad stage 0x07 sidetone_biq_b01_hi upper byte of b01 coefficient for first sidetone biquad stage 0x08 sidetone_biq_b02_lo lower byte of b02 coefficient for first sidetone biquad stage 0x09 sidetone_biq_b02_hi upper byte of b02 coefficient for first sidetone biquad stage 0x0a sidetone_biq_a10_lo lower byte of a10 coefficient for second sidetone biquad stage 0x0b sidetone_biq_a10_hi upper byte of a10 coefficient for second sidetone biquad stage 0x0c sidetone_biq_a11_lo lower byte of a11 coefficient for second sidetone biquad stage 0x0d sidetone_biq_a11_hi upper byte of a11 coefficient for first sidetone biquad stage 0x0e sidetone_biq_a12_lo lower byte of a12 coefficient for first sidetone biquad stage 0x0f sidetone_biq_a12_hi upper byte of a12 coefficient for first sidetone biquad stage 0x10 sidetone_biq_b11_lo lower byte of b11 coef ficient for first sidetone biquad stage 0x11 sidetone_biq_b11_hi upper byte of b11 coefficient for second sidetone biquad stage 0x12 sidetone_biq_b12_lo lower byte of b12 coefficient for second sidetone biquad stage 0x13 sidetone_biq_b12_hi upper byte of b12 coefficient for second sidetone biquad stage 0x14 sidetone_biq_a20_lo lower byte of a20 coefficient for third sidetone biquad stage 0x15 sidetone_biq_a20_hi upper byte of a20 coefficient for third sidetone biquad stage 0x16 sidetone_biq_a21_lo lower byte of a21 coefficient for third sidetone biquad stage z - 1 a 0 0 a 0 1 a 0 2 z - 1 b 0 1 b 0 2 z - 1 z - 1 z - 1 a 1 0 a 1 1 a 1 2 z - 1 b 1 1 b 1 2 z - 1 z - 1 z - 1 a 2 0 a 2 1 a 2 2 z - 1 b 2 1 b 2 2 z - 1 z - 1 x [ n ] y [ n ]
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 39 of 171 ? 2016 dialog semiconductor 0x17 sidetone_biq_a21_hi upper byte of a21 coefficient for third sidetone biquad stage 0x18 sidetone_biq_a22_lo lower byte of a22 coefficient for third sidetone biquad stage 0x19 sidetone_biq _a22_hi upper byte of a22 coefficient for third sidetone biquad stage 0x1a sidetone_biq_b21_lo lower byte of b21 coefficient for third sidetone biquad stage 0x1b sidetone_biq_b21_hi upper byte of b21 coefficient for third sidetone biquad stage 0x1c sidetone_biq_b22_lo lower byte of b22 coefficient for third sidetone biquad stage 0x1d sidetone_biq_b22_hi upper byte of b22 coefficient for third sidetone biquad stage
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 40 of 171 ? 2016 dialog semiconductor 9.3.3 tone g enerator the tone generator contains two independent sine wave generators (swgs). each swg can generate a sine wave at a frequency (freq) from approximately 1 hz to 12 khz according to the programmed 16 - bit value: freq[15:0] = 2 16 * f swg /12000, for sr2 = (8, 12, 16, 24, 32, 48,96) khz freq[15:0] = 2 16 * f swg /11025, for sr2 = (11 .025, 22.05, 44.1, 88.2) khz the da7217 should not be programmed with frequency greater than the nyquist frequency. nyquist frequency = sr2/2 for the first swg, the freq value is stored in two 8 - bit registers as freq1_u = freq[15:8] and freq1_l = freq[7:0]. the second swg frequency is programmed in the same w ay using freq2_u and freq2_l . the output of the tone gen erator can come from either of the swgs, or from a combination of both of them as specified by swg_sel . in addition the tone generator can produce standard dual tone multi - frequency (dtmf) tones using the two swgs if dtmf_en = 1 and the required keypad value is programmed in dtmf_reg as shown in table 34 . table 34 : dtmf t ones c orresponding to dtmf_reg v alue the tone generator can produce 1, 2, 3, 4, 8, 16, or 32 beeps, or a continuous beep, as determined by beep_cycles . each beep has an on period from 10 ms to 2 s as programmed in beep_on_per and an off period from 10 ms to 2 s as programmed in beep_off_per . the tone generator is started by setting the start_stopn bit, and is halted by clearing this bit. if start_stopn is cleared, the tone generator stops at the completion of the current beep cycle or at the next zero - cross if the number of beeps is set to continuous ( beep_cycles = 110 or = 111). the start_stopn bit is automatically cleared once the programmed number of beep cycles has been completed. 9.3.4 the tone generator c an also be used to produce an s - ramp by setting swg_sel to 0x03. system c ontroller the system control ler (sc) automates the sequencing of the multiple bloc ks required to set up one or more particular audio paths. it is an optional feature, and operates by performing register writes with optimal sequencing and timing, thus eliminating pops and clicks. the inputs are controlled using system_modes_input , and the outputs are controlled using system_modes_output . writing to the mode_submit field of either of these registers will cause the system controller (sc) to process both input and output paths. when the sc is activated by asserting the mode_submit field, all of the register - writes that are required by the selected sub systems are performed automatically. each sub - system is brought up, or down, in the correct order to avoid pops and clicks. in addition, within each sub system, the component parts are brought up in the correct pop - free and click - free sequence. swg2 freq (hz) swg1 frequency (hz) 1209 1336 1477 1633 697 0x1 0x2 0x3 0xa 770 0x4 0x5 0x6 0xb 852 0x7 0x8 0x9 0xc 941 0xe 0x0 0xf 0xd
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 41 of 171 ? 2016 dialog semiconductor 9.3.5 output p rocessing 9.3.5.1 output f ilters figure 15 : output f ilters b lock d iagram there is a stereo output filter chain that is used to process signals to be sent to the stereo dac. the signals from the digital mixer (at sr2 rate) can be processed through a high - pass filter, a fixed 5 - band equalizer and a 5 - stage biquad filter. they can also be combined with signals from the sidetone filter (at 4 * sr2 rate). left and right channels of the output filter can be controlled independently. the left channel of the output filter is enabled using out_1l_filter_en and i s muted using out_1l_mute_en . gain ramping is enabled using out_1l_ramp_en . if out_1l_subrange_en is also set, the ramping process will step though much finer gain increments . the 5 - stage biquad filter is select ed using out_1l_biq_5stage_sel . the gain of the left channel can be set in the range of - 83.25 db to +108 db in 0.75 db steps using out_1l_gain . the right channel of the output filter is controlled in the same way. 9.3.5.2 high - p ass f ilter the output high - pass filters (hpfs) are controlled using out_1_hpf_filter_ctrl . in music mode out_1_voice_en m ust be set to 0 and the hpf corner frequency is set using out_1_audio_hpf_corner . in voice mode, out_1_voice_en must be set to 1, in which case the hpf corner frequency is set using out_1_voice_hpf_corner . the value of the hpf corner frequency also depends on the output sample rate (sr2) as shown in table 35 . the right channel of the hpf is controlled in the same way. o u t _ 1 _ f i l t e r 5 b e q s d m d w a s d m d w a f s 2 2 f s 2 4 f s 2 8 f s 2 f s d m 5 b i q u a d 5 b i q u a d 5 b e q o u t _ 1 l _ b i q _ s e l o u t _ 1 r _ b i q _ s e l f r o m s i d e t o n e f r o m s i d e t o n e f r o m m i x e r t o h e a d p h o n e s
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 42 of 171 ? 2016 dialog semiconductor table 35 : output h igh - p ass f ilter s ettings (adc in high - p ower m ode) in_1_voice_en out_1_voice_hpf_corn er out_1_audio_hpf_corn er . sr1 s ample r ate (khz) 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 0 00 0.33 0.46 0.5 0.67 0.92 1 1.33 1.84 2 3.68 4 01 0.67 0.92 1 1.33 1.84 2 2.67 3.68 4 7.35 8 10 1.33 1.84 2 2.67 3.68 4 5.33 7.35 8 14.7 16 11 2.67 3.68 4 5.33 7.35 8 10.67 14.7 16 29.4 32 1 000 2.5 3.45 3.75 5 6.89 7.5 10 voice hpf not available for sample rates above 32 khz. 001 25 34.5 37.5 50 68.9 75 100 010 50 68.9 75 100 137.8 150 200 011 100 137.8 150 200 275.6 300 400 100 150 206.7 225 300 413.4 450 600 101 200 275.6 300 400 551.3 600 800 110 300 413.4 450 600 826.9 900 1200 111 400 551.3 600 800 1102.5 1200 1600 table 36 : output h igh - p ass f ilter s ettings (adc in low - p ower m ode) in_1_voice_en out_1_voice_hpf_corne r in_1_audio_hpf_corner sr1 s ample r ate (khz) 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 0 00 0.33 0.46 0.5 0.67 0.92 1 32 khz sample rate not available in low - power mode 1.84 2 88.2 khz and 96 khz sample rates not available in low - power mode 01 0.67 0.92 1 1.33 1.84 2 3.68 4 10 1.33 1.84 2 2.67 3.68 4 7.35 8 11 2.67 3.68 4 5.33 7.35 8 14.7 16 1 000 2.5 in low - power mode, the voice hpf is only available at a sample rate of 8 khz 001 25 010 50 011 100 100 150 101 200 110 300 111 400
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 43 of 171 ? 2016 dialog semiconductor 9.3.5.3 5 - b and equalizer the output filters can provide gain or attenuation in each of five separate (fixed) frequency bands using the 5 - band equalizer (eq). the equalizer , for both left and right channels, is enabled using out_1_eq_en . the gain or attenuation of the first frequency band is programmable from - 10.5 db to 12 .0 db in 1.5 db steps using out_1_eq_band1 . the other four bands are programmable in the same way using out_1_eq_band2 , out_1_eq_band3 , out_1_eq_band4 , and out_1_eq_band5 . the center or cut - off frequency of each of the five bands depends on t he output sample rate (sr2) as shown in table 37 . the 5 - band eq and the 5 - band biquad filter can be used at the same time for greater filtering contro l. table 37 : output 5 - band equalizer c entre and c ut - o ff f requencies for equalizer bands 1 and 5, the cut - off frequency depends on the gain setting. the figures quoted in this table refer to the C 1 db point with the band gain set to C 3 db sr2 (khz) cente r / cut - o ff f requency (hz) a t p rogrammed s etting band 1 c ut - o ff band 2 c ente r band 3 c ente r band 4 c ente r band 5 c ut - o ff 8 0 99 493 1528 4000 11.025 0 136 680 2106 5512 12 0 148 740 2293 6000 16 0 96 440 2128 8000 22.05 0 133 607 2933 11025 24 0 145 660 3191 12000 32 0 95 418 1797 16000 44.1 0 131 576 2386 22050 48 0 143 627 2596 24000 88.2 n/a n/a n/a n/a n/a 96 n/a n/a n/a n/a n/a note the 5 - band equalizer is only available for sample rates up to 48 khz. the frequency response of the 5 - band equalizer at sample rate of 48 khz is shown graphically in figure 16 to figure 20 : the cut - off for equalizer bands 1 and 5 is dependent on gain setting. the figures quoted in table 37 refer to the - 1 db point with the band gain set to - 3 db
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 44 of 171 ? 2016 dialog semiconductor figure 16 : equalizer f ilter b and 1 f requency r esponse at fs = 48 khz figure 17 : equalizer f ilter b and 2 f requency r esponse at fs = 48 khz figure 18 : equalizer f ilter b and 3 f requency r esponse at fs = 48 khz
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 45 of 171 ? 2016 dialog semiconductor figure 19 : equalizer f ilter b and 4 f requency r esponse at fs = 48 khz figure 20 : equalizer f ilter b and 5 f requency r esponse at fs = 48 khz 9.3.5.4 5 - s tage b iquad f ilter the stereo 5 - stage biquad filter can be used to provide more flexible filtering of the output signal than can be achieved using the 5 - band equalizer . the biquad filters can be used for the implementation of low - pass, high - pass or notch filters. the 5 - band eq and the 5 - band biquad filter can be used at the same time for greater filtering control. the biquad filter is enabled using out_1_biq_5stage_filter_en a nd can be muted using out_1_biq_5stage_mute_en . the biquad filter on each channel can be selected independently using out_1l_biq_5stage_sel and out_1r_biq_5stage_sel in the out_1l_filter_ctrl and out_1r_filter_ctrl registers.
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 46 of 171 ? 2016 dialog semiconductor figure 21 : single b iquad f ilter s tage each of the five biquad stages has five 16 - bit coefficients a0, a1, a2, b1 and b2 as shown in figure 21 . for the five stages the coefficients are numbered a00, a01 and so on as shown in figure 22 . the filter sections are implemented using a direct form one architecture which implements the transfer function shown in figure 21 : figure 22 : cascade of f ive b iquad f ilter s tages the biquad filters in both left and right channels share the same set of coefficients. each of the coefficients is stored using two 8 - bit registers in a dedicated address space. all of the coefficients are programmed by first writing the coefficient data value to out_1_biq_5stage_data and then the coefficient address to out_1_biq_5stage_addr . the address location for each of the coefficients is described in table 38 . each of the 16 - bit coefficients are twos complement values that can be programmed in the ran ge of - 2 (0x8000) to +2 (0x7fff (0)). c hecks should be made to ensure that the pre - programmed coefficients result in a stable transfer filter function. the full numeric range of the coefficients is - 2 to +1.999938964843750. k e y z - 1 = d e l a y o f o n e u n i t ( i n p u t t o o u t p u t ) a n = f e e d - f o r w a r d c o e f f i c i e n t s ( r a n g e + 2 t o - 2 ) b n = f e e d b a c k c o e f f i c i e n t s ( r a n g e + 2 t o - 2 ) z - 1 a 0 a 1 a 2 z - 1 b 1 b 2 z - 1 z - 1 x [ n ] y [ n ] 2 2 1 1 2 2 1 1 0 1 4 4 3 3 ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? z b z b z a z a z a z a a z h z - 1 a 0 0 a 0 1 a 0 2 z - 1 b 0 1 b 0 2 z - 1 z - 1 z - 1 a 1 0 a 1 1 a 1 2 z - 1 b 1 1 b 1 2 z - 1 z - 1 z - 1 a 2 0 a 2 1 a 2 2 z - 1 b 2 1 b 2 2 z - 1 z - 1 z - 1 a 3 0 a 3 1 a 3 2 z - 1 b 3 1 b 3 2 z - 1 z - 1 z - 1 a 4 0 a 4 1 a 4 2 z - 1 b 4 1 b 4 2 z - 1 z - 1 x [ n ] y [ n ]
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 47 of 171 ? 2016 dialog semiconductor table 38 : output 5 - s tage b iquad f ilter c oefficient a ddress m ap address out_1_biq_5s tage_addr name description 0x00 out_1_biq_a00_lo lower byte of a00 coefficient for first output biquad stage biquad filter 1 0x01 out_1_biq_a00_hi upper byte of a00 coefficient for first output biquad stage 0x02 out_1_biq_a01_lo lower byte of a01 coefficient for first output biquad stage 0x03 out_1_biq_a01_hi upper byte of a01 coefficient for first output biquad stage 0x04 out_1_biq_a02_lo lower byte of a02 coefficient for first output biquad stage 0x05 out_1_biq_a02_hi upper byte of a02 coefficient for first output biquad stage 0x06 out_1_biq_b01_lo lower byte of b01 coefficient for first output biquad stage 0x07 out_1_biq_b01_hi upper byte of b01 coefficient for first output biquad stag e 0x08 out_1_biq_b02_lo lower byte of b02 coefficient for first output biquad stage 0x09 out_1_biq_b02_hi upper byte of b02 coefficient for first output biquad stage 0x0a out_1_biq_a10_lo lower byte of a10 coefficient for second output biquad stage biquad filter 2 0x0b out_1_biq_a10_hi upper byte of a10 coefficient for second output biquad stage 0x0c out_1_biq_a11_lo lower byte of a11 coefficient for second output biquad stage 0x0d out_1_biq_a11_hi upper byte of a11 coefficient for second output biquad stage 0x0e out_1_biq_a12_lo lower byte of a12 coefficient for second output biquad stage 0x0f out_1_biq_a12_hi upper byte of a12 coefficient for second output biquad stage 0x10 out_1_biq_b11_lo lower byte of b11 coefficient for second output biquad stage 0x11 out_1_biq_b11_hi upper byte of b11 coefficient for second output biquad stage 0x12 out_1_biq_b12_lo lower byte of b12 coefficient for second output biquad stage 0x13 out_1_biq_b12_hi upper byte of b12 coefficient for second output biquad stage 0x14 out_1_biq_a20_lo lower byte of a20 coefficient for third output biquad stage biquad filter 3 0x15 out_1_biq_a20_hi upper byte of a20 coefficient for third output biquad stage 0x16 out_1_biq_a21_lo lower byte of a21 coefficient for third output biquad stage 0x17 out_1_biq_a21_hi upper byte of a21 coefficient for third output biquad stage 0x18 out_1_biq_a22_lo lower byte of a22 coefficient for third output biquad stage 0x19 out_1_biq_a22_hi upper byte of a22 coefficient for third output biquad stage 0x1a out_1_biq_b21_lo lower byte of b21 coefficient for third output biquad stage 0x1b out_1_biq_b21_hi upper byte of b21 coefficient for third output biquad stage 0x1c out_1_biq_b22_lo lower byte of b22 coefficient for third output biquad stage 0x1d out_1_biq_b22_hi upper byte of b22 coefficient for third output biquad stage 0x1e out_1_biq_a30_lo lower byte of a30 coefficient for fourth output biquad stage biquad filter 4 0x1f out_1_biq_a30_hi upper byte of a30 coefficient for fourth output biquad stage 0x20 out_1_biq_a31_lo lower byte of a31 coefficient for fourth output biquad stage 0x21 out_1_biq_a31_hi upper byte of a31 coefficient for fourth output biquad stage 0x22 out_1_biq_a32_lo lower byte of a32 coefficient for fourth output biquad stage 0x23 out_1_biq_a32_hi upper byte of a32 coefficient for fourth output biquad stage 0x24 out_1_biq_b01_lo lower byte of b31 coefficient for fourth output biquad stage
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 48 of 171 ? 2016 dialog semiconductor address out_1_biq_5s tage_addr name description 0x25 out_1_biq_b31_hi upper byte of b31 coefficient for fourth output biquad stage 0x26 out_1_biq_b32_lo lower byte of b32 coefficient for fourth output biquad stage 0x27 out_1_biq_b32_hi upper byte of b32 coefficient for fourth output biquad stage 0x28 out_1_biq_a40_lo lower byte of a40 c oefficient for fifth output biquad stage biquad filter 5 0x29 out_1_biq_a40_hi upper byte of a40 coefficient for fifth output biquad stage 0x2a out_1_biq_a41_lo lower byte of a41 coefficient for fifth output biquad stage 0x2b out_1_biq_a41_hi upper byte of a41 coefficient for fifth output biquad stage 0x2c out_1_biq_a42_lo lower byte of a42 coefficient for fifth output biquad stage 0x2d out_1_biq_a42_hi upper byte of a42 coefficient for fifth output biquad stage 0x2e out_1_biq_b41_lo lower byte of b41 coefficient for fifth output biquad stage 0x2f out_1_biq_b41_hi upper byte of b41 coefficient for fifth output biquad stage 0x30 out_1_biq_b42_lo lower byte of b42 coefficient for fifth output biquad stage 0x31 out_1_biq_b42_hi upper byte of b42 coefficient for fifth output biquad stage 9.3.5.5 output d ynamic r ange e xtension the output dynamic range extension (dre) block extends the range of the da7217 . dre can be enabled on either left, right or both output channels using dgs_enable . the input signal level at which the dre starts swapping gains can be set in the range of - 90 db to 0 db in 6 db steps using dgs_signal_lvl . to prevent clipping, the input signal level at which all of the applied dre steps are removed can be set in the range of - 42 db to 0 db in 6 db steps using dgs_anticlip_lvl . the maximum number of 1.5 db gain steps that the dre is allowed to apply can be controlled using dgs_steps . the response time of the leaky integrator used to track the signal level at the input of the dre is determined by the fraction of the signal added at each step. the fall rate is set by the fraction added when the signal is smaller than the current average, which can be programmed in the range 1/65536 to 1/4 using dgs_fall_coeff . the rise rate is set by the fraction added when the signal is larger than the current average, which can be programmed in the range 1/16384 to 1 using dgs_rise_coeff . ramping of any changes in gain levels is enabled by setting dgs_ramp_en = 1. when ramping is being performed, the changes in gain are made in 1.5 db steps, with the maximum number of 1.5 db steps controlled by dgs_steps . finer control of the ramping steps is provided if dgs_subr_en = 1. if dgs_subr_en = 1, each gain change of 1.5 db is performe d in smaller steps. it is possible to disable the ramping of the 1.5 db gain steps by setting dgs_ramp_en = 0, and similarly it is possible to disable the sub - ranging between the 1.5 db gain steps by setting dgs_subr_en = 0. note that clearing either of these two bits is likely to produce unacceptable audio artefacts such as pops and clicks. 9.3.5.6 dac n oise g ate the dac noise gate can be used to automatically mute the outputs when the average signal level at the output of both left and right channel dacs falls below a programmed noise threshold for longer than a programmed hold time. the dac noise gate is enabled using dac_ng_en . the threshold below which the noise gate is activated can be set in the range of - 102 db to - 60 db in 6 db steps using dac_ng_on_threshold . the
da7217 ultra - low power stereo codec datasheet revision 2.5 01 sep 2016 cfr0011 - 120 - 00 49 of 171 ? 2016 dialog semiconductor threshold above which the noise gate deactivates can be set in the same range using dac_ng_off_threshold . it is recommended to set dac_ng_off_threshold > dac_ng_on_threshold to provide some hysteresis. the number of samples for which the dac output signal must be below the on - threshold before the noise gate is activated can be set to 256, 512, 1024 or 2048 using dac_ng_setup_time . the noise gate is deactivated as soon as the signal level rises above the off threshold. prior to muting the output the gain is ramped down to minimum, and after un - muting the output the gain is ramped back up to its original value. the ramp rates can be adjusted using dac_ng_rampdn_rate and dac_ng_rampup_rate . 9.3.5.7 digital m ixer the da7217 codec contains a flexible digital mixer. any or all of the se ven digital inputs (four input filters, one tone generator, and two dai inputs) can be routed to any or all of the six digital outputs (output filter 1 and output filter 2, and four dai outputs) with a programmable gain on each of the 42 possible paths. th e names of the registers that specify the data source, and the data output, take the form
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